1. Field of the Invention
This invention relates to a self shift drive system for a gas discharge panel, especially for an AC driven type gas discharge panel known as a plasma display panel, and more particularly to a self shift drive system therefor, of inexpensive construction.
2. Description of the Prior Art
As is well-known in the art, in a plasma display panel, electrodes covered with dielectric layers, such as of a low-melting-point glass, are disposed in contact with a discharge gas space having sealed therein an ionizable gas such as neon or the like; an alternating sustain voltage is applied between adjacent or opposing ones of the electrodes; and once a discharge is produced by applying a write voltage higher than a firing voltage, the discharge is continuously maintained by the alternating sustain voltage to enable a display by the discharge glow.
Further, there has already been proposed a self shift drive system such that the discharge spot is sequentially shifted by connecting the electrodes to buses energized by multiphase, such as three-phase, ones voltages, or the like, applied to the buses in succession. FIG. 1 is a block diagram showing one example of such a self shift drive system. A plasma display panel 1 comprises common electrodes y1 to y7 connected to a common bus Y, write electrodes w1 to w7 disposed opposite to the common electrodes y1 to y7 to intersect them at right angles and shift electrodes a1, b1, c1, d1, a2, b2, . . . connected to buses A, B, C and D and periodically energized from these buses in the order A, B, C and D. The electrodes are all covered with dielectric layers.
Reference numeral 2 indicates a character generator; 3 and 4 designate shift registers; 5 denotes an oscillator; 6 identifies a frequency divider; 7 represents a phase shifter for shifting the output phase .phi.A of the oscillator 5 through 180.degree. to .phi.B; 8 shows each of plural write drivers; 9 and 10 refer to groups of AND circuits; 11 designates each of plural shift drivers for applying a shift voltage to the buses A to D; and 12 identifies a driver for applying a voltage to a common bus Y.
The output from the oscillator 5 is frequency divided by the frequency divider 6 and its frequency divided output drives the shift register 4. Since there are four buses A to D, the shift register 4 is a 4-bit shift register and the output from each of its stages, through a corresponding AND gate 10, drives an associated shift driver 11 and a shift voltage pulse train thereby is sequentially applied to the buses A to D in accordance with a desired shift speed. Further, since the driver 12 is driven by the output from the phase shifter 7, a voltage composed of a pulse train, which is displaced 180.degree. apart in phase from the voltage applied to the buses A to D, is applied to the bus Y.
Upon application of display information to the character generator 2, a write signal is produced in accordance with the output from the shift register 3. In the case of displaying one character with 5.times.7 dots, a character spacing corresponding to two bits can be provided by implementing the shift register 3, for example, with a 7-bit shift register.
Each write driver 8 is driven in accordance with a write signal derived from the character generator 2 to apply a write voltage to its respective, and thereby, one of the write electrodes w1 to w7, whereby a discharge spot is produced between the write electrode and the common electrodes y1 to y7, and the discharge spot is sequentially shifted to the right by switching of the shift voltage applied to the buses A to D.
FIG. 2A is a diagram illustrating the principal parts of the aforesaid drivers 8 and 11, and FIG. 2B illustrates the driver 12; FIGS. 3A and 3B illustrate waveform diagrams for explaining their operations. A transistor QS is turned on at the time of the output .phi.A and transistors QA to QD, comprising the shift drivers, are turned on at the time of an output .phi.A from the oscillator 5 only while outputs from the stages of the shift register 4 corresponding to them exist. Further, a transistor QE is turned on by the output .phi.A from the oscillator 5 and a transistor QY1 connected to the bus Y and a transistor QY2 are turned on by outputs .phi.B and .phi.B from the phase shifter 7, respectively. Voltages V.sub.s and V.sub.E bear such a relation that V.sub.s &gt;V.sub.E, and the voltage V.sub.E is selected at an erasing level.
Consequently, the write electrodes w1 to w7 are supplied with a voltage VW shown in FIG. 3A and the buses A to D and Y are supplied with voltages VA to VD and VY, respectively. Namely, in the period from an instant t.sub.1 to t.sub.3 during which the output from a first stage of the shift register 4 corresponding to the bus A is "1", the transistor QA is driven at the timing of the output .phi.A from the oscillator 5 to apply a pulse voltage 0 to +V.sub.s to the bus A. In the following period from the instant t.sub.3 to t.sub.4, that is, while a similar shift pulse voltage is applied to the other buses, the output from the first stage of the shift register 4 is "0", so that the transistor QA is held in its off state, during which, however, a voltage +V.sub.E to +V.sub.s is applied to the bus A by the transistor QE which is turned on and off by the output .phi.A from the oscillator 5. The level at this time is an erasing level. In a similar manner, the other buses B to D are also supplied with pulse voltages indicated by VB to VD, respectively, and the shift pulse voltages applied to the buses A to D sequentially overlap in time corresponding to the period from the instant t.sub.2 to t.sub.3.
While the transistors QA to QD making up the shift driver 11 are sequentially driven by the output from the shift register as described above, if a discharge spot is produced in a certain discharge cell, a discharge cell immediately subsequent thereto, which is impressed with the voltage 0 to +V.sub.s, is supplied with ions, electrons and metastable atoms from the discharge spot in the preceding discharge cell to produce a discharge spot therein at the voltage V.sub.s and, on the other hand, the preceding discharge cell is automatically supplied with a voltage of the erasing level by the reduction of the output from the shift register 4 corresponding to this cell to "0", so that the discharge is stopped and a wall voltage produced by the discharge is also extinguished. Thus, the preceding discharge cell is cleared before the application of the shift voltage of the next period and made ready for receiving new information.
FIG. 3B shows, on enlarged scale, one part of each of the voltages VB and VY. A voltage indicated by VCL is applied to a discharge cell formed between the shift electrode connected to the bus B and the common electrode connected to the bus Y. For example, in the case of a sustain voltage having a peak voltage 330V, the voltage V.sub.s is 165V and the voltage V.sub.E is 60V and each transistor is required to have a withstand voltage higher than 165V. Further, it is necessary that each voltage has a relatively high frequency of about several hundred KHz and that its rise is sharp. Transistors of such high withstand voltage and high-speed operation are expensive and inevitably increase the cost of the drive circuit of the plasma display panel. Further, high-speed shifting requires application of the voltage V.sub.2 -V.sub.E of the erasing level by the transistor QE for positively erasing the wall voltage remaining in the discharge cell after shifting, as shown, for example, in FIG. 2, and also necessitates the provision of the transistor QE for that purpose.